Semiconductor processing has moved towards the production of smaller and smaller devices having greater computing capability. The reduction in device size and increase in power has resulted in a higher density of transistors in a given unit area. Enhanced semiconductor fabrication techniques, such as silicon on insulator (SOI) processing, tend to increase metal wiring requirements due to significant resistance increases in device components such as the transistor source and drain.
Specific applications, such as arrays, are often impacted by the amount of wiring needed to fully enable the application. Wiring in semiconductor devices is generally configured in multiple planes, especially when multiple devices are configured in a dense pattern. Metal wiring in a given plane of the device reduces the amount of real estate available in that plane and can put severe constraints on device performance. These problems can undermine the overall objective to fabricate smaller, more densely packed devices having superior performance.
Prior publications which are exemplary of silicon on insulator process technology include Iwamatsu, U.S. Pat. No. 5,294,821. Iwamatsu discloses silicon-on-insulator technology which is intended to provide more uniform electrical characteristics including a reduction in breakdown voltage. Iwamatsu proposes a device having active layers diffused into the substrate to stabilize the electrical characteristics of the device.
Tyson et al., U.S. Pat. No. 5,145,802, discloses a silicon-on-insulator circuit which includes a set of buried body ties that provide a local ohmic contact to the transistor bodies disposed on an insulating layer. This is intended to provide a path for holes generated by impact ionization and also act as a potential shield between the substrate and the transistor sources.
Kang et al., U.S. Pat. No. 5,286,670, teaches a method of manufacturing a semiconductor device having buried elements with electrical characteristics. Kang uses a complex system buried electrical elements in the substrate bonding the substrate to the silicon that is to become the SOI region. One exemplary use for the buried elements is as capacitors in memory cells.
However, these publications do not address or resolve many of the problems which arise with increased device density. In fact, certain of these publications, such as Kang et al, add to the complexity of device fabrication without resolving concerns of wiring density.
As a result, there is a need for processes and devices which allow for the reduction of metal wiring in a given plane thereby allowing for greater device performance and greater design flexibility in high density applications.